Defect and Fault Tolerance in VLSI Systems Proceedings of the International Symposium, Albuquerque, New Mexico, 1999
| Author/creator | IEEE Staff |
| Other author | IEEE Xplore (Online service) |
| Format | Electronic |
| Publication Info | Los Alamitos : IEEE Computer Society Press |
| Description | 375 p. 22.000 x 015.000 cm. |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) Conference Proceedings |
| Supplemental Content | Full text available from IEEE Conference Proceedings Archive |
| Subjects |
| Summary | Annotation Papers from a November 1999 symposium cover areas of yield, testing techniques, built-in self-test architectures, fault modeling and simulation, design for testing, self-checking processing units and systems, self-checking memories and interconnections, diagnosis, and reconfiguration. Specific topics include a zero aliasing built-in self-test technique for delay fault testing, novel control pattern generators for interconnect testing with boundary scan, optimal vector selection for low power BIST, and fast signature simulation for PPSFP simulators. Other topics are erasure error correction with hardware correction, and reconfiguration of two-dimensional meshes embedded in faulty hypercubes. Lacks a subject index. Annotation copyrighted by Book News, Inc., Portland, OR |
| Access restriction | Available only to authorized users. |
| Technical details | Mode of access: World Wide Web |
| Genre/form | Electronic books. |
| ISBN | 9780769503257 |
| ISBN | 076950325X (Trade Paper) Active Record |
| Standard identifier# | 9780769503257 |
| Stock number | 00029433 |