Proceedings International Workshop on Memory Technology, Design, and Testing / edited by F. Lombardi, R. Rajsuman, and T. Wik ; sponsored by IEEE Computer Society, IEEE Computer Society Technical Committee on Test Technology, IEEE Computer Society Technical Committee on VLSI ; in cooperation with IEEE Solid State Circuits Council.

Author/creator IEEE International Workshop on Memory Technology, Design, and Testing
Format Electronic
Publication InfoLos Alamitos, Calif. : IEEE Computer Society Press,
Descriptionix, 103 p. : ill. ; 28 cm.
Supplemental ContentFull text available from IEEE Electronic Library (IEL)
Supplemental ContentFull text available from IEEE Conference Proceedings Archive
Supplemental ContentFull text available from IEEE Electronic Library (IEL) Conference Proceedings
Subjects
Semiconductor storage devices--Testing. --Congresses.
Random access memory--Congresses.

Other author/creatorLombardi, Fabrizio, 1955-
Other author/creatorRajsuman, Rochit.
Other author/creatorWik, T. (Thomas)
Other author/creatorIEEE Computer Society. Test Technology Technical Committee.
Other author/creatorIEEE Computer Society. Technical Committee on VLSI.
Other author/creatorIEEE Xplore (Online service)
Cover title Records of the IEEE International Workshop on Memory Technology, Design and Testing
Portion of title Memory Technology, Design and Testing
Portion of title MTDT'97
Contents Matching memory to the power of personal computers / R. Foss -- A low-cost, high performance three-dimensional memory module technology / A. Glaser ... [et al.] -- High speed circuit techniques in a 150MHz 64M SDRAM / V. Lines ... [et al.] -- An analysis of (linked) addressed decoder faults / A. van de Goor, G. Gaydadjiev -- SRAM yield estimation in the early stage of the design cycle / V. Kim, T. Chen -- False write through and un-restored write electrical level fault models for SRAMs / R. Adams, E. Cooley -- A defect-tolerant DRAM employing a hierarchical redundancy scheme, built-in self-test and self-reconfiguration / D. Niggemeyer, J. Otterstedt, M. Redeker -- Formal verification of memory arrays using symbolic trajectory evaluation / M. Pandey, R. Bryant -- A product development flow with metrics for memory designs / S. Hegde, I. Pal, K. Rao -- A low-power high storage capacity structure for GaAs MESFET ROM / R. Kanan ... [et al.] -- Use of selective precharge for low-power on the match lines of content-addressable memories / C. Zukowski, S. Wang -- An open notation for memory tests / A. Offerman, A. van de Goor -- Testing memory modules in SRAM-based configurable FPGAs / W. Huang ... [et al.] -- Memory array testing through a scannable configuration / S. Yano, N. Ishiura -- A high-speed parallel sensing scheme for multi-level non-volatile memories / C. Calligaro ... [et al.].
General note"August 11-12, 1997, San Jose, California"--Cover.
General note"IEEE Order Plan Catalog Number 95TB100159"--T.p. verso.
General note"IEEE Computer Society Order Number PR08099"--T.p. verso.
Bibliography noteIncludes bibliographical references and index.
Access restrictionAvailable only to authorized users.
Technical detailsMode of access: World Wide Web
Genre/formElectronic books.
LCCN 97202128
ISBN0818680997 (paper)
ISBN0818681004 (case)
ISBN0818681012 (microfiche)

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