19th IEEE VLSI Test Symposium, 2001, Marina Del Rey, CA
| Other author | IEEE Xplore (Online service) |
| Format | Electronic |
| Publication Info | Los Alamitos : IEEE Computer Society Press |
| Description | 456 p. 27.000 x 021.000 cm. |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) Conference Proceedings |
| Subjects |
| Summary | Annotation Collects 58 papers from the April/May 2001 symposium that explore new approaches in the testing of electronic circuits and systems. Key areas in testing are discussed, such as BIST, analog measurement, fault tolerance, diagnosis methods, scan chain design, memory test and diagnosis, and test data compression and compaction. Also on the program are sessions on emerging areas that are gaining prominence, including low power testing, testing high speed circuits on low cost testers, processor based self test techniques, and core- based system-on-chip testing. Some of the topics are robust and low cost BIST architectures for sequential fault testing in datapath multipliers, a method for measuring the cycle-to-cycle period jitter of high-frequency clock signals, fault equivalence identification using redundancy information and static and dynamic extraction, and test scheduling for minimal energy consumption under power constraints. No subject index. c. Book News Inc. |
| Access restriction | Available only to authorized users. |
| Technical details | Mode of access: World Wide Web |
| Genre/form | Electronic books. |
| ISBN | 9780769511221 |
| ISBN | 0769511228 (Trade Paper) Active Record |
| Standard identifier# | 9780769511221 |
| Stock number | 00029433 |