2002 International Workshop on Innovative Architecture (IWIA 2002) Innovative Architecture for Future Generation High-Performance Processors and Systems
| Author/creator | Veidenbaum, Alex Editor |
| Other author | Joe, Kazuki Editor |
| Other author | IEEE Xplore (Online service) |
| Format | Electronic |
| Publication Info | I E E E [Imprint] Los Alamitos : IEEE Computer Society Press |
| Description | 128 p. ill 28.000 x 022.000 cm. |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) Conference Proceedings |
| Subjects |
| Summary | Annotation Gathers the 12 papers presented during the January 2002 workshop on high performance computing, with an emphasis on low power design and network processing. Among the topics are reducing power with an L0 instruction cache using history-based prediction, tight nonlinear loop timing estimation, multigrain parallel processing for JPEG encoding on a single chip multiprocessor, and a low latency, high bandwidth network interface prototype for PC clusters. No subject index. Annotation copyrighted by Book News, Inc., Portland, OR |
| Access restriction | Available only to authorized users. |
| Technical details | Mode of access: World Wide Web |
| Genre/form | Electronic books. |
| LCCN | 2002727137 |
| ISBN | 9780769516356 |
| ISBN | 0769516351 (Trade Paper) Active Record |
| Standard identifier# | 9780769516356 |
| Stock number | PR01635 00029433 |