IEEE International High-Level Design Validation and Test Workshop Proceedings, 8-10 November 2000, Berkeley, California
| Author/creator | IEEE Computer Society, Technical Council on Test Technology Staff |
| Other author | IEEE Computer Society, Design Automation Technical Committee Staff. |
| Other author | IEEE Xplore (Online service) |
| Format | Electronic |
| Publication Info | Los Alamitos : IEEE Computer Society Press |
| Description | x, 179 p. ill 28.000 x 022.000 cm. |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) Conference Proceedings |
| Subjects |
| Summary | Annotation Proceedings of a November 2000 workshop, with papers in sections on advances in high-level test, validation and test for microprocessor designs, hardware/software co-validation, formal verification techniques and applications, issues in high-level design validation, formal verification techniques, and advances in simulation-based verification. Specific topics include hardware/software co-debugging for reconfigurable computing, statistical behavior of branch coverage in testing behavioral VHDL models, system level testability analysis using Petri nets, and data flow based cache prediction using local simulation. Lacks a subject index. Annotation copyrighted by Book News, Inc., Portland, OR |
| Access restriction | Available only to authorized users. |
| Technical details | Mode of access: World Wide Web |
| Genre/form | Electronic books. |
| LCCN | 00110249 |
| ISBN | 9780769507866 |
| ISBN | 0769507867 (Trade Paper) Active Record |
| Standard identifier# | 9780769507866 |
| Stock number | 00029433 |