Defect and Fault-Tolerance in VLSI Systems, 1995 Workshop
| Other author | IEEE Xplore (Online service) |
| Format | Electronic |
| Publication Info | Los Alamitos : IEEE Computer Society Press |
| Description | 320 p. 24.000 x 017.000 cm. |
| Supplemental Content | Full text available from IEEE Conference Proceedings Archive |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) Conference Proceedings |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) |
| Subjects |
| Summary | Annotation An invited talk recounts Intel's experience with increasing die yield through CAD algorithms, and a panel discussion examines tools for the extracting of critical areas for a yield analysis of VLSI design. Others of the 34 papers cover critical area analysis, defect sensitivity and reliability, fault tolerant architectures and arrays, yield projection and enhancement, fault tolerant and testing techniques, and self-checking and coding techniques. No subject index. Annotation copyright by Book News, Inc., Portland, OR |
| Access restriction | Available only to authorized users. |
| Technical details | Mode of access: World Wide Web |
| Genre/form | Electronic books. |
| LCCN | 10636722 |
| ISBN | 9780818671074 |
| ISBN | 0818671076 (Trade Cloth) Out of Stock Indefinitely |
| Standard identifier# | 9780818671074 |
| Stock number | PR07107 00029433 |
Availability
| Library | Location | Call Number | Status | Item Actions |
|---|---|---|---|---|
| Electronic Resources | ✔ Available |