Verilog HDL Conference, 1994

Other author IEEE Xplore (Online service)
Format Electronic
Publication InfoLos Alamitos : IEEE Computer Society Press
Description136 p.
Supplemental ContentFull text available from IEEE Electronic Library (IEL)
Supplemental ContentFull text available from IEEE Conference Proceedings Archive
Supplemental ContentFull text available from IEEE Electronic Library (IEL) Conference Proceedings
Subjects
Computers--Congresses.
Verilog (Computer Hardware Description Language)

Summary Annotation Proceedings of a conference held in Santa Clara, California, March 1994. Papers are divided into sessions on language and compilation, simulation, applications, designs and methodologies, and modeling applications. Topics discussed include Verilog Netlist as an exchange language, optimizing compiled Verilog, fully specified verification simulation, finite state machine trace analysis program, timing modeling of datapath layout for synthesis, and Verilog simulation of Xilinx designs. No index. Annotation copyright by Book News, Inc., Portland, OR
Access restrictionAvailable only to authorized users.
Technical detailsMode of access: World Wide Web
Genre/formElectronic books.
LCCN 93074849
ISBN9780818656552
ISBN0818656557 (Trade Paper) Out of Stock Indefinitely
Standard identifier# 9780818656552
Stock number5655 00029433

Availability

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Electronic Resources ✔ Available