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010 a| 2008050653;

020 a| 9780521859721 (hardback);

020 a| 0521859727 (hardback);

035 a| (WaSeSS)ssj0000341710;

049 a| EREEa| NEHH;

050 00 a| TK7874.58b| .P73 2009;

082 00 a| 621.3815/482| 22;

245 00 a| Practical design verificationh| [electronic resource] /c| edited by Dhiraj K. Pradhan, Ian G. Harris.;

260 a| Cambridge, UK ;a| New York :b| Cambridge University Press,;

300 a| xi, 276 p. :b| ill. ;c| 26 cm.;

504 a| Includes bibliographical references and index.;

505 0 a| Model checking and equivalence checking / Masahiro Fujita -- Transaction-level system modeling / Daniel Gajski and Samar Abdi -- Response checkers, monitors, and assertions / Harry Foster -- System debugging strategies / Wayne H. Wolf -- Test generation and coverage metrics / Ernesto Sánchez, Giovanni Squillero, and Matteo Sonza Reorda -- SystemVerilog and Vera in a verification flow / Shireesh Verma and Ian G. Harris -- Decision diagrams for verification / Maciej Ciesielski, Dhiraj K. Pradhan, and Abusaleh M. Jabir -- Boolean satisfiability and EDA applications / Joao Marques-Silva.;

506 a| Available only to authorized users.;

538 a| Mode of access: World Wide Web;

650 0 a| Integrated circuitsx| Verification.=| ^A399142;

655 0 a| Electronic books.=| ^A491897;

700 1 a| Pradhan, Dhiraj K.=| ^A1198265;

700 1 a| Harris, Ian G.=| ^A1209182;

856 40 z| Full text available from Ebook Central - Academic Completeu| https://ebookcentral.proquest.com/lib/eastcarolina/detail.action?docID=451928;

947 a| (OCoLC)ocn268793465;

949 a| CLICK ON WEB ADDRESSw| ASISh| JOYNER188;

949 a| CLICK ON WEB ADDRESSw| ASISh| HSL77;

949 a| CLICK ON WEB ADDRESSw| ASISh| JMUSIC60;

596 a| 1 3 4;

998 a| 4743736;

999 a| CLICK ON WEB ADDRESSw| ASISc| 1i| 4743736-1001l| JNETm| JOYNERr| Ys| Yt| JNESSBKu| 8/22/2017x| EBOOKz| JERESOURCE;

999 a| CLICK ON WEB ADDRESSw| ASISc| 1i| 4743736-2001l| HSLELECm| HSLr| Ys| Yt| HEBKu| 8/22/2017x| EBOOKz| HERESOURCE;

999 a| CLICK ON WEB ADDRESSw| ASISc| 1i| 4743736-3001l| MNETm| JMUSICr| Ys| Yt| MNESSBKu| 8/22/2017x| EBOOKz| JERESOURCE;

Practical design verification / edited by Dhiraj K. Pradhan, Ian G. Harris.

Other author	Pradhan, Dhiraj K.
Other author	Harris, Ian G.
Format	Electronic
Publication Info	Cambridge, UK ; New York : Cambridge University Press,
Description	xi, 276 p. : ill. ; 26 cm.
Supplemental Content	Full text available from Ebook Central - Academic Complete
Subjects	Integrated circuits--Verification.

Contents	Model checking and equivalence checking / Masahiro Fujita -- Transaction-level system modeling / Daniel Gajski and Samar Abdi -- Response checkers, monitors, and assertions / Harry Foster -- System debugging strategies / Wayne H. Wolf -- Test generation and coverage metrics / Ernesto Sánchez, Giovanni Squillero, and Matteo Sonza Reorda -- SystemVerilog and Vera in a verification flow / Shireesh Verma and Ian G. Harris -- Decision diagrams for verification / Maciej Ciesielski, Dhiraj K. Pradhan, and Abusaleh M. Jabir -- Boolean satisfiability and EDA applications / Joao Marques-Silva.
Bibliography note	Includes bibliographical references and index.
Access restriction	Available only to authorized users.
Technical details	Mode of access: World Wide Web
Genre/form	Electronic books.
LCCN	2008050653
ISBN	9780521859721 (hardback)
ISBN	0521859727 (hardback)

Practical design verification / edited by Dhiraj K. Pradhan, Ian G. Harris.

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